The present invention relates to a SOI-MOS field effect transistor and a method of forming the same.
A silicon-on-insulator structure comprises a single crystal silicon layer provided on an insulation layer and may be formed by a separation by implantation oxygen method or a method of bonding silicon substrates. A MOS field effect transistor is formed in the single crystal silicon layer. The SOI-MOS field effect transistor may be classified into two types in view of the thickness of the single crystal silicon layer. The first one is a thick film SOI-MOS field effect transistor and the second one is a thin film SOI-MOS field effect transistor. The single crystal silicon layer of the thick film SOI-MOS field effect transistor has a thickness, for example, not less than 1000 nanometers. The single crystal silicon layer of the thin film SOI-MOS field effect transistor has a thickness in the range of, for example, about 30 nanometers to about 200 nanometers.
The thin film SOI-MOS field effect transistor is superior in low parasitic capacitance, low junction leakage current, complete device isolation, and anti-soft error properties, for which reason the thin film SOI-MOS field effect transistor is suitable for high speed performance, low power consumption, high density integration and high reliability.
The thin film SOI-MOS field effect transistor is, however, engaged with a serious problem with floating-body effects. The thin film SOI structure makes it difficult to fix a potential of a channel region. This allows that excess carriers generated by an impact ionization phenomenon in the vicinity of the drain region are accumulated in a lower region of the body region. This accumulation of the excess carrier in the body region causes the floating-body effects such as a drop of drain breakdown voltage and kink effects on current-voltage characteristics.
In order to settle the above problems with the substrate floating effects, it had been proposed to withdraw the excess carriers from the body region through a body contact region which is electrically connected to the body region. FIG. 1 is a fragmentary plane view illustrative of this first conventional SOI-MOS field effect transistor having a body contact region electrically connected to the channel region for withdrawing the excess carriers from the body region through the body contact region. FIG. 2A is a fragmentary cross sectional elevation view illustrative of the first conventional SOI-MOS field effect transistor taken along a B-B' line of FIG. 1. FIG. 2B is a fragmentary cross sectional elevation view illustrative of the first conventional SOI-MOS field effect transistor taken along a C-C' line of FIG. 1.
The first conventional SOI-MOS field effect transistor is provided which comprises the following elements. A buried silicon oxide layer 102 is provided on a silicon substrate 101. A monocrystal silicon layer is provided on the buried silicon oxide layer 102 to form a silicon-on-insulator structure. The monocrystal silicon layer is surrounded by field oxide films 113. The monocrystal silicon layer further comprises the following parts. A body region 103 of a first conductivity type is selectively formed on the buried silicon oxide layer 102. A first diffusion region 104 of a second conductivity type acts as one of source and drain regions and is selectively formed on the buried silicon oxide layer 102 and in one side of the body region 103. A second diffusion region 105 of the second conductivity type acts as another one of the source and drain regions and is selectively formed on the buried silicon oxide layer 102 and in an opposite side of the body region 103 so that the channel region 103 is positioned between the first and second diffusion regions 104 and 105. An isolation layer 110 is selectively formed on the buried silicon oxide layer 102 and is bounded with the first diffusion region 104 so that the first diffusion region 104 is positioned between the body region 103 and the isolation layer 110. A body contact region 111 of the first conductivity type is selectively formed on the buried silicon oxide layer 102 and is bounded with the isolation layer 110 so that the body contact region 111 is isolated by the isolation layer 110 from the first diffusion region 104. A pair of carrier path regions 112 of the first conductivity type is selectively formed on the buried silicon oxide layer 102 so that the carrier path regions 112 extend along first opposite sides of the monocrystal silicon layer in a channel length direction, where the first opposite sides are distanced from each other in a channel width direction along B-B' line of FIG. 1 perpendicular to the channel length direction along C-C' line. The carrier path regions 112 are bounded with the field oxide films 113, whereby each of the carrier path regions 112 is in contact directly with the body contact region 111, the first and second diffusion regions 104 and 105, the isolation layer 110 and the body region 103. A gate insulation film 106 is selectively provided on the body region 103. A gate electrode 107 is provided on the gate insulation film 106 and over the body region 103. Lightly doped silicon regions 109 of the second conductivity type having a lower impurity concentration than impurity concentrations of the first and second diffusion regions 104 and 105 are provided on the buried silicon oxide layer 102 and between the body region 103 and the first diffusion region 104 and between the body region 103 and the second diffusion region 105. Side wall insulation films 108 are provided on opposite side walls of the gate electrode 107 and on top surfaces of the lightly doped silicon regions 109. An inter-layer insulator 114 covers the gate electrode 107, the first and second diffusion regions 104 and 105, the isolation layer 110, the body contact region 111, and the carrier path regions 112. A contact layer 121 is formed in a contact hole formed in the inter-layer insulator 114 and over the body contact region 111 so that the contact layer 121 is in contact with the body contact region 111. An interconnection layer 122 extends over the inter-layer insulator 114 and also is connected with the contact layer 121 so that the interconnection layer 122 is electrically connected through the contact layer 121 to the body contact region 111.
The body region 103 mid the body contact region 111 are electrically connected to each other through the carrier path regions 112, The first and second diffusion regions 104 and 105 are electrically isolated by p-n junctions from the carrier path regions 112 and from the body region 103 as well as from the body contact region 111. Any excess carriers generated in the body region 103 due to an impact ionization phenomenon are allowed to be withdrawn through the carrier path regions 112, the body contact region 111 and the contact layer 121 to the interconnection layer 122. The above carrier path structure makes the SOI-MOS field effect transistor free from the various problems caused by the floating-body effects.
The above body contact region 111 of the first conductivity type has a higher impurity concentration than an impurity concentration of the body region 103. The carrier path layers 112 of the first conductivity type have an impurity concentration which is equal to or higher than an impurity concentration of the body region 103 but is lower than an impurity concentration of the body contact region 111.
The isolation layer 110 isolates the body contact region 111 of the first conductivity type from the first diffusion layer 104 of the second conductivity type so as to makes the SOI-MOS field effect transistor free from the problem with a drop of junction break down voltage.
In the above SOI-MOS field effect transistor, the reduction in thickness of the single crystal silicon layer provided on the buried silicon layer improves sub-threshold characteristics and suppresses the short channel effects. The reduction in thickness of the single crystal silicon layer provided on the buried silicon layer, however, raises problems with increase in resistance of the diffusion regions acting as the source and drain regions. The increase in resistance of the diffusion regions acting as the source and drain regions makes prevents the semiconductor integrated circuit from exhibiting the required high speed performance.
In order to settle the problem with increased resistance of the diffusion regions acting as the source/drain regions, it is effective to selectively form metal silicide layers in upper regions of the diffusion regions acting as the source/drain regions.
The source/drain diffusion regions with the metal silicide layers may usually be formed as follows.
After a gate electrode and source and drain regions have been formed in the normal or well known method, then a refractory metal layer or a noble metal layer is entirely formed by a sputtering method A heat treatment is carried out to cause a silicidation reaction of metal with silicon to form silicide layers on the surface regions of the source/drain diffusion regions and the gate electrode by use of the self-alignment techniques. Namely, self-aligned silicide layers or salicide layers are selectively formed on the source/drain diffusion regions and the gate electrode. Unreacted parts of the metal layer are removed.
If the above formation method for the metal silicide layers on the gate electrode and the source/drain diffusion regions is applied to the above described SOI-MOS field effect transistor shown in FIGS. 1, 2A and 2B, then the following serious problems are raised.
As illustrated in FIGS. 3 and 4, if the metal layer is entirely deposited which covers the field oxide film 113, the carrier path regions 112, the body contact region 111, the isolation layer 110, the source and drain diffusion regions 104 and 105, the side wall oxide films 108 and the gate electrode 107 and subsequently a heat treatment is carried out to cause the silicidation reaction of metal with silicon, then a silicide layer 123, 124 is formed which extends over the body contact region 111, the carrier path regions 112, the source drain diffusion regions 104 and 105 and the gate electrode 107. The unreacted parts of the metal layer are then removed. However, the source and drain diffusion regions 104 and 105 of the second conductivity type are electrically connected through the metal suicide layer 123, 124 to the carrier path regions 112 of the first conductivity type and also to the body contact region 111 of the first conductivity type. Since the body region 103 of the first conductivity type is electrically connected to the carrier path regions 112 of the first conductivity type, then the source and drain diffusion regions 104 and 105 of the second conductivity type are also electrically connected through the silicide layer 123, 124 and the carrier path region 112 to the body region 103. The metal silicide layer 123, 124 provides a short circuit between the first conductivity type silicon regions such as the body region 103 and the body contact region 111 and the second conductivity type silicon regions such as the source/drain diffusion regions 104 and 105. As a result, the SOI-MOS field effect transistor shown in FIGS. 3 and 4 could no longer exhibit any required functions.
In the above circumstances, it had been required to develop a novel SOI-MOS field effect transistor free from the above problems.